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one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ultralow distortion, wide bandwidth voltage feedback op amps ad9631/ad9632 these characteristics position the ad9631/ad9632 ideally for driving flash as well as high resolution adcs. additionally, the balanced high impedance inputs of the voltage feedback archi- tecture allow maximum flexibility when designing active filters. the ad9631 is offered in industrial (C40 c to +85 c) and mili- tary (C55 c to +125 c) temperature ranges and the ad9632 in industrial. industrial versions are available in plastic dip and soic; mil versions are packaged in cerdip. ?0 ?30 100k 100m 10m 1m 10k ?0 ?0 ?10 ?0 frequency ?hz harmonic distortion ?dbc v o = 2v p? v s = 5v r l = 500 w 2nd harmonic 3rd harmonic figure 1. ad9631 harmonic distortion vs. frequency, g = +1 features wide bandwidth ad9631, g = +1 ad9632, g = +2 small signal 320 mhz 250 mhz large signal (4 v p-p) 175 mhz 180 mhz ultralow distortion (sfdr), low noise C113 dbc typ @ 1 mhz C95 dbc typ @ 5 mhz C72 dbc typ @ 20 mhz +46 dbm 3rd order intercept @ 25 mhz 7.0 nv / ? hz spectral noise density high speed slew rate 1300 v/ m s settling 16 ns to 0.01%, 2 v step 3 v to 5 v supply operation 17 ma supply current applications adc input driver differential amplifiers if/rf amplifiers pulse amplifiers professional video dac current to voltage baseband and video communications pin diode receivers active filters/integrators/log amps product description the ad9631 and ad9632 are very high speed and wide band- width amplifiers. they are an improved performance alternative to the ad9621 and ad9622. the ad9631 is unity gain stable. the ad9632 is stable at gains of two or greater. utilizing a voltage feedback architecture, the ad9631/ad9632s excep- tional settling time, bandwidth, and low distortion meet the requirements of many applications which previously depended on current feedback amplifiers. its classical op amp structure works much more predictably in many designs. a proprietary design architecture has produced an amplifier that combines many of the best characteristics of both current feed- back and voltage feedback amplifiers. the ad9631 and ad9632 exhibit exceptionally fast and accurate pulse response (16 ns to 0.01%) as well as extremely wide small signal and large signal bandwidth and ultralow distortion. the ad9631 achieves C72 dbc at 20 mhz and 320 mhz small signal and 175 mhz large signal bandwidths. functional block diagram 8-pin plastic mini-dip (n), cerdip (q), and so (r) packages 1 2 3 4 8 7 6 5 ad9631/32 nc ?nput +input ? s nc +v s output nc (top view) nc = no connect
C2C ad9631a ad9632a parameter conditions min typ max min typ max units dynamic performance bandwidth (C3 db) small signal v out 0.4 v p-p 220 320 180 250 mhz large signal 1 v out = 4 v p-p 150 175 155 180 mhz bandwidth for 0.1 db flatness v out = 300 mv p-p 9631, r f = 140 w ; 9632, r f = 425 w 130 130 mhz slew rate, average +/C v out = 4 v step 1000 1300 1200 1500 v/ m s rise/fall time v out = 0.5 v step 1.2 1.4 ns v out = 4 v step 2.5 2.1 ns settling time to 0.1% v out = 2 v step 11 11 ns to 0.01% v out = 2 v step 16 16 ns harmonic/noise performance 2nd harmonic distortion 2 v p-p; 20 mhz, r l = 100 w C64 C57 C54 C47 dbc r l = 500 w C72 C65 C72 C65 dbc 3rd harmonic distortion 2 v p-p; 20 mhz, r l = 100 w C76 C69 C74 C67 dbc r l = 500 w C81 C74 C81 C74 dbc 3rd order intercept 25 mhz +46 +41 dbm noise figure r s = 50 w 18 14 db input voltage noise 1 mhz to 200 mhz 7.0 4.3 nv ? hz input current noise 1 mhz to 200 mhz 2.5 2.0 pa ? hz average equivalent integrated input noise voltage 0.1 mhz to 200 mhz 100 60 m v rms differential gain error (3.58 mhz) r l = 150 w 0.03 0.06 0.02 0.04 % differential phase error (3.58 mhz) r l = 150 w 0.02 0.04 0.02 0.04 degree phase nonlinearity dc to 100 mhz 1.1 1.1 degree dc performance 2 , r l = 150 w input offset voltage 3 310 25 mv t min Ct max 13 8 mv offset voltage drift 10 10 m v/ c input bias current 2 7 2 7 m a t min Ct max 10 10 m a input offset current 0.1 3 0.1 3 m a t min Ct max 55 m a common-mode rejection ratio v cm = 2.5 v 70 90 70 90 db open-loop gain v out = 2.5 v 46 52 46 52 db t min Ct max 40 40 db input characteristics input resistance 500 500 k w input capacitance 1.2 1.2 pf input common-mode voltage range 3.4 3.4 v output characteristics output voltage range, r l = 150 w 3.2 3.9 3.2 3.9 v output current 70 70 ma output resistance 0.3 0.3 w short circuit current 240 240 ma power supply operating range 3.0 5.0 6.0 3.0 5.0 6.0 v quiescent current 17 18 16 17 ma t min Ct max 21 20 ma power supply rejection ratio t min Ct max 50 60 56 66 db notes 1 see max ratings and theory of operation sections of data sheet. 2 measured at a v = 50. 3 measured with respect to the inverting input. specifications subject to change without notice. ( v s = 5 v; r load = 100 w ; a v = 1 (ad9631); a v = 2 (ad9632), unless otherwise noted) rev. a ad9631/ad9632Cspecifications electrical characteristics
ad9631/ad9632 rev. a C3C absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 v voltage swing bandwidth product . . . . . . . . . . 550 v mhz internal power dissipation 2 plastic package (n) . . . . . . . . . . . . . . . . . . . . . . . . 1.3 watts small outline package (r) . . . . . . . . . . . . . . . . . . . 0.9 watts input voltage (common mode) . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . 1.2 v output short circuit duration . . . . . . . . . . . . . . . . . . . . . . observe power derating curves storage temperature range n, r . . . . . . . . . C65 c to +125 c operating temperature range (a grade) . . . C40 c to +85 c lead temperature range (soldering 10 sec) . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air: 8-pin plastic package: q ja = 90 c/watt 8-pin soic package: q ja = 140 c/watt maximum power dissipation the maximum power that can be safely dissipated by these de- vices is limited by the associated rise in junction temperature. the maximum safe junction temperature for plastic encapsu- lated devices is determined by the glass transition temperature of the plastic, approximately +150 c. exceeding this limit tem- porarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceed- ing a junction temperature of +175 c for an ex tended period can result in device failure. while the ad9631 and ad9632 are internally short circuit pro- tected, this may not be sufficient to guarantee that the maxi- mum junction temperature (+150 c) is not exceeded under all conditions. to ensure proper operation, it is necessary to ob- serve the maximum power derating curves. 2.0 0 ?0 80 1.5 0.5 ?0 1.0 0 10 ?0 ?0 ?0 20 30 40 50 60 70 90 ambient temperature ? c maximum power dissipation ?watts t j = +150 c 8-pin mini-dip package 8-pin soic package figure 2. plot of maximum power dissipation vs. temperature warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although these devices feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. metalization photo dimensions shown in inches and (mm). connect substrate to Cv s . 0.046 (1.17) 3 +in 4 ? s 6 out ?n 2 +v s 7 ad9631 0.050 (1.27) 0.046 (1.17) 0.050 (1.27) 3 +in 4 ? s 6 out ?n 2 +v s 7 ad9632 ordering guide temperature package package model range description option* ad9631an C40c to +85 c plastic dip n-8 ad9631ar C40 c to +85 c soic r-8 ad9631(smd) C55 c to +125 c cerdip q-8 ad9631-eb evaluation board ad9632an C40 c to +85 c plastic dip n-8 ad9632ar C40 c to +85 c soic r-8 AD9632-EB evaluation board *n = plastic dip; q = cerdip; r= soic (small outline integrated circuit).
ad9631/ad9632 rev. a C4C r f +v s pu lse generator r l = 100 w ? s v in v out 0.1 m f 10 m f ad9631 3 2 7 6 0.1 m f 10 m f 4 t r /t f = 350ps 130 w r t 49.9 w figure 3. noninverting configuration, g = +1 figure 4. large signal transient response; v o = 4 v p-p, g = +1, r f = 250 w figure 5. small signal transient response; v o = 400 mv p-p, g = +1, r f = 140 w 100 w +v s ? s 0.1 m f 10 m f ad9631 3 2 7 6 0.1 m f 10 m f 4 130 w r t 49.9 w r f r l = 100 w v out t r /t f = 350ps pulse generator v in figure 6. inverting configuration, g = C1 figure 7. large signal transient response; v o = 4 v p-p, g = C1, r f = r in = 267 w figure 8. small signal transient response; v o = 400 mv p-p, g = C1, r f = r in = 267 w ad9631Ctypical characteristics
ad9631/ad9632 rev. a C5C r f pulse generator +v s r l = 100 w ? s v in v out 0.1 m f 10 m f ad9632 3 2 7 6 0.1 m f 10 m f 4 t r /t f = 350ps r in 130 w r t 49.9 w figure 9. noninverting configuration, g = +2 figure 10. large signal transient response; v o = 4 v p-p, g = +2, r f = r in = 422 w figure 11. small signal transient response; v o = 400 mv p-p, g = +2, r f = r in = 274 w 100 w r f +v s r l = 100 w ? s v out 0. 1 m f 10 m f ad9632 3 2 7 6 0.1 m f 10 m f 4 t r /t f = 350ps v in pu lse generator 130 w r t 49.9 w figure 12. inverting configuration, g= C1 figure 13. large signal transient response; v o = 4 v p-p, g = C1, r f = r in = 422 w , r t = 56.2 w figure 14. small signal transient response; v o = 400 mv p-p, g = C1, r f = r in = 267 w , r t = 61.9 w ad9632Ctypical characteristics
ad9631/ad9632 rev. a C6C ad9631Ctypical characteristics 1 ? ? 1m 10m 1g 100m ? ? ? ? ? ? ? 0 frequency ?hz gain ?db v s = 5v r l = 100 w v o = 300mv p-p r f 150 w r f 100 w r f 200 w r f 50 w figure 15. ad9631 small signal frequency response g = +1 0.1 ?.4 ?.9 1m 10m 500m 100m ?.5 ?.6 ?.7 ?.8 ?.3 ?.2 ?.1 0 frequency ?hz gain ?db v s = 5v r l = 100 w g = +1 v o = 300mv p-p r f 120 w r f 140 w r f 150 w r f 100 w figure 16. ad9631 0.1 db flatness, n package (for r package add 20 w to r f ) 60 10 10k 100k 10m 1m 30 20 40 50 frequency ?hz gain ?db 0 ?0 100m 1g 100 20 0 ?0 40 60 80 ?0 ?00 ?20 ?0 ?0 90 70 80 ?0 phase margin ?degrees phase gain figure 17. ad9631 open-loop gain and phase margin vs. frequency, r l = 100 w value of feedback resistor (r f ) ? w ?db bandwidth ?mhz 450 250 20 240 400 300 40 350 200 220 180 160 140 120 100 80 60 n package r package r f 130 w ad9631 v s = 5v r l = 100 w gain = +1 r l figure 18. ad9631 small signal C3 db bandwidth vs. r f 1 ? ? 1m 10m 500m 100m ? ? ? ? ? ? ? 0 frequency ?hz output ?db v s = 5v v o = 4v p-p r l = 100 w r f 250 w r f = 50 w to 250 w by 50 w figure 19. ad9631 large signal frequency response, g = +1 1 ? ? 1m 10m 1g 100m ? ? ? ? ? ? ? 0 frequency ?hz gain ?db r f 267 w v s = 5v r l = 100 w v o = 300mv p-p figure 20. ad9631 small signal frequency response, g = C1
ad9631/ad9632 rev. a C7C ?0 ?30 100k 100m 10m 1m 10k ?0 ?0 ?10 ?0 frequency ?hz harmonic distortion ?dbc v o = 2v p-p v s = 5v r l = 500 w g = +1 2nd harmonic 3rd harmonic figure 21. ad9631 harmonic distortion vs. frequency, r l = 500 w ?0 ?30 100k 100m 10m 1m 10k ?0 ?0 ?10 ?0 frequency ?hz v o = 2v p-p v s = 5v r l = 100 w g = +1 2nd harmonic 3rd harmonic harmonic distortion ?dbc figure 22. ad9631 harmonic distortion vs. frequency, r l = 100 w 50 30 10 100 25 20 35 40 45 frequency ?mhz intercept ?+dbm 60 55 20 40 80 60 figure 23. ad9631 third order intercept vs. frequency 0.10 ?.10 ?.05 0.00 0.05 diff gain ?% 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 0.05 ?.05 0.00 0.10 diff phase ?degrees ?.10 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th figure 24. ad9631 differential gain and phase error, g = +2, r l = 150 w 0.3 ?.3 0 ?.2 0 ?.1 0.2 0.1 80 60 40 20 settling time ?ns error ?% 70 50 30 10 figure 25. ad9631 short-term settling time, 2 v step, r l = 100 w 0.3 ?.2 0.1 ?.1 1 0 0.2 10 9 7 6 5 4 3 2 settling time ?? error ?% 8 0 figure 26. ad9631 long-term settling time, 2 v step, r l = 100 w
ad9631/ad9632 rev. a C8C 7 2 ? 1m 10m 1g 100m 1 0 ? ? 3 4 5 6 r f 325 r f 425 r f 125 r f 225 frequency ?hz gain ?db v s = 5v r l = 100 w v o = 300mv p-p figure 27. ad9632 small signal frequency response, g = +2 0.1 ?.4 ?.9 1m 10m 100m ?.5 ?.6 ?.7 ?.8 ?.3 ?.2 ?.1 0 output ?db r f 375 r f 425 r f 275 r f 325 frequency ?hz v s = 5v r l = 100 w g = +2 v o = 300mv p-p figure 28. ad9632 0.1 db flatness, n package (for r package add 20 w to r f ) 65 25 ?5 10k 100k 1g 100m 10m 1m 35 45 55 ? 5 15 frequency ?hz 60 20 30 40 50 ?0 0 10 a ol ?db ?0 ?50 0 50 100 ?00 ?50 ?00 phase ?degrees gain phase figure 29. ad9632 open-loop gain and phase margin vs. frequency, r l = 100 w 200 150 100 250 300 350 550 500 450 400 350 300 250 200 150 value of r f ,r in ? w ?db bandwidth ?mhz n package r package v s = 5v r l = 100 w gain = +2 r f ad9632 r l r in 100 w 49.9 w figure 30. ad9632 small signal C3 db bandwidth vs. r f , r in 7 2 ? 1m 10m 500m 100m 1 0 ? ? 3 4 5 6 frequency ?hz output ?db r f 525 r f 125 w to 525 w by 100 w v s = 5v v o = 4v p-p r l = 100 w figure 31. ad9632 large signal frequency response, g = +2 1 ? ? 1m 10m 1g 100m ? ? ? ? ? ? ? 0 frequency ?hz gain ?db v s = 5v r l = 100 w v o = 300mv p-p r f , r in 267 w figure 32. ad9632 small signal frequency response, g = C1 ad9632Ctypical characteristics
ad9631/ad9632 rev. a C9C ?0 ?30 100k 100m 10m 1m 10k ?0 ?0 ?10 ?0 frequency ?hz harmonic distortion ?dbc v o = 2v p-p v s = 5v r l = 500 w g = +2 2nd harmonic 3rd harmonic figure 33. ad9632 harmonic distortion vs. frequency, r l = 500 w ?0 ?30 100k 100m 10m 1m 10k ?0 ?0 ?10 ?0 frequency ?hz harmonic distortion ?dbc v o = 2v p-p v s = 5v r l = 100 w g = +2 2nd harmonic 3rd harmonic figure 34. ad9632 harmonic distortion vs. frequency, r l = 100 w 50 30 10 10 100 25 20 15 35 40 45 frequency ?mhz intercept ?+dbm figure 35. ad9632 third order intercept vs. frequency 0.04 ?.04 ?.02 0.00 0.02 diff gain ?% 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 0.02 ?.02 0.00 0.04 diff phase ?degrees ?.04 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th figure 36. ad9632 differential gain and phase error g = +2, r l = 150 w 0.2 ?.3 0 ?.2 010 20 30 40 50 60 70 80 ?.1 0.1 settling time ?ns error ?% figure 37. ad9632 short-term settling time 2 v step, r l = 100 w 0.3 ?.2 0.1 ?.1 09 8 7 6 5 4 3 2 1 0 0.2 settling time ?? error ?% 10 figure 38. ad9632 long-term settling time 2 v step, r l = 100 w
rev. a C10C 24 18 3 100 100k 10k 1k 10 21 12 15 6 9 frequency ?hz v s = 5v input noise voltage ?nv/ ? hz figure 39. ad9631 noise vs. frequency 80 70 60 50 40 30 20 10 0 75 65 55 45 35 25 15 5 10k 100k 1g 100m 10m 1m frequency ?hz psrr ?db ?srr +psrr figure 40. ad9631 psrr vs. frequency 100 90 80 70 60 50 40 30 20 100k 1g 100m 10m 1m frequency ?hz cmrr ?db v s = 5v d v cm = 1v r l = 100 w figure 41. ad9631 cmrr vs. frequency 17 13 3 100 100k 10k 1k 10 15 9 11 5 7 frequency ?hz input noise voltage ?nv/ ? hz v s = 5v figure 42. ad9632 noise vs. frequency 80 70 60 50 40 30 20 10 0 75 65 55 45 35 25 15 5 10k 100k 1g 100m 10m 1m frequency ?hz psrr ?db ?srr +psrr figure 43. ad9632 psrr vs. frequency 100 90 80 70 60 50 40 30 20 100k 1g 100m 10m 1m frequency ?hz cmrr ?db v s = 5v d v cm = 1v r l = 100 w figure 44. ad9632 cmrr vs. frequency ad9631/ad9632Ctypical characteristics
ad9631/ad9632 rev. a C11C 1000 10 0.01 100k 100m 10m 1m 10k 1 0.1 100 frequency ?hz r out ? w v s = 5v gain = +1 figure 45. ad9631 output resistance vs. frequency 1000 10 0.01 100k 100m 10m 1m 10k 1 0.1 100 frequency ?hz r out ? w v s = 5v gain = +2 figure 46. ad9632 output resistance vs. frequency 4.1 3.3 140 3.5 3.4 ?0 ?0 3.7 3.6 3.8 3.9 4.0 120 100 80 60 40 20 0 ?0 junction temperature ? c output swing ?volts v s = 5v r l = 150 +v out |? out | r l = 50 +v out |? out | } } figure 47. ad9631/ad9632 output swing vs. temperature 1350 350 140 650 450 ?0 550 ?0 950 750 850 1050 1150 1250 120 100 80 60 40 20 0 ?0 junction temperature ? c open-loop gain ?v/v ad9632 ad9631 +a ol ? ol +a ol ? ol figure 48. open-loop gain vs. temperature 76 56 140 62 58 ?0 60 ?0 68 64 66 70 72 74 120 100 80 60 40 20 0 ?0 junction temperature ? c psrr ? ?b ad9632 ad9631 ad9632 ad9631 ?srr +psrr ?srr +psrr figure 49. psrr vs. temperature ?8 ?6 140 ?2 ?8 ?0 ?0 ?0 ?6 ?4 120 80 60 40 100 20 0 ?0 junction temperature ? c cmrr ? ?b ?mrr +cmrr figure 50. ad9631/ad9632 cmrr vs. temperature
rev. a C12C ad9631/ad9632Ctypical characteristics 21 14 140 17 15 ?0 16 ?0 20 18 19 120 100 80 60 40 20 0 ?0 junction temperature ? c supply current ?ma ad9631 ad9632 ad9631 ad9632 6v 6v 5v 5v figure 51. supply current vs. temperature ?.0 ?.0 140 ?.0 ?.5 ?0 ?0 ?.0 ?.5 ?.5 ?.0 ?.5 120 100 80 60 40 20 0 ?0 junction temperature ? c input offset voltage ?mv ad9632 ad9631 v s = 5v v s = 6v v s = 5v v s = 6v figure 52. input offset voltage vs. temperature 220 0 7 60 20 ? 40 ? 120 80 100 140 160 180 200 5 4 3 2 1 ? ? ? ? ? 0 6 100 20 0 10 50 30 40 60 70 80 90 input offset voltage ?mv count percent cumulative 3 wafer lots count = 1373 freq. dist figure 53. ad9631 input offset voltage distribution 250 180 140 210 190 ?0 200 ?0 240 220 230 120 100 80 60 40 20 0 ?0 junction temperature ? c short circuit current ?ma ad9631 ad9632 sink source sink source figure 54. short circuit current vs. temperature 2.0 ?.0 140 ?.0 ?.5 ?0 ?0 0.0 ?.5 0.5 1.0 1.5 120 100 80 60 40 20 0 ?0 junction temperature ? c input bias current ?? ad9631 ad9632 +i b +i b ? b ? b figure 55. input bias current vs. temperature 0 7 60 20 ? 40 ? 120 80 100 140 160 180 5 4 3 2 1 ? ? ? ? ? 0 6 100 20 0 10 50 30 40 60 70 80 90 input offset voltage ?mv count percent cumulative 3 wafer lots count = 573 freq. dist figure 56. ad9632 input offset voltage distribution
ad9631/ad9632 rev. a C13C theory of operation general the ad9631 and ad9632 are wide bandwidth, voltage feed- back amplifiers. since their open-loop frequency response fol- lows the conventional 6 db/octave roll-off, their gain bandwidth product is basically constant. increasing their closed-loop gain results in a corresponding decrease in small signal bandwidth. this can be observed by noting the bandwidth specification between the ad9631 (gain of 1) and ad9632 (gain of 2). the ad9631/ad9632 typically maintain 65 degrees of phase mar- gin. this high margin minimizes the effects of signal and noise peaking. feedback resistor choice the value of the feedback resistor is critical for optimum perfor- mance on the ad9631 (gain +1) and less critical as the gain in- creases. therefore, this section is specifically targeted at the ad9631. at minimum stable gain (+1), the ad9631 provides optimum dynamic performance with r f = 140 w . this resistor acts only as a parasitic suppressor against damped rf oscillations that can occur due to lead (input, feedback) inductance and parasitic capacitance. this value of r f provides the best combination of wide bandwidth, low parasitic peaking, and fast settling time. in fact, for the same reasons, a 100C130 w resistor should be placed in series with the positive input for other ad9631 noninverting and all ad9631 inverting configurations. the cor- rect connection is shown in figures 57 and 58. +v s ? s v in 100?30 w 0.1 m f 10 m f 6 7 2 4 3 0.1 m f 10 m f r f r g r in v out g = 1 + r f r g ad9631/32 r term figure 57. noninverting operation +v s ? s v in 100?30 w 0.1 m f 10 m f 6 7 2 4 3 0.1 m f 10 m f r f r g r term v out g = ? r f r g ad9631/32 r in figure 58. inverting operation when the ad9631 is used in the transimpedance (i to v) mode, such as in photodiode detection, the value of r f and diode ca- pacitance (c i ) are usually known. generally, the value of r f se- lected will be in the k w range, and a shunt capacitor (c f ) across r f will be required to maintain good amplifier stability. the value of c f required to maintain optimal flatness (<1 db peak- ing) and settling time can be estimated as: c f @ (2 w o c i r f 1)/ w o 2 r f 2 [] 1/2 where w o is equal to the unity gain bandwidth product of the amplifier in rad/sec, and c i is the equivalent total input capacitance at the inverting input. typically w o = 800 10 6 rad/sec (see open-loop frequency response curve (fig- ure 17). as an example, choosing r f = 10 k w and c i = 5 pf, requires c f to be 1.1 pf (note: c i includes both source and parasitic circuit capacitance). the bandwidth of the amplifier can be es- timated using the c f calculated as: f 3 db @ 1. 6 2 p r f c f r f v out ad9631 c f c i i i figure 59. transimpedance configuration
ad9631/ad9632 rev. a C14C for general voltage gain applications, the amplifier bandwidth can be closely estimated as: f 3 db @ w o 2 p 1 + r f r g ? ? ? ? ? ? this estimation loses accuracy for gains of +2/C1 or lower due to the amplifiers damping factor. for these low gain cases, the bandwidth will actually extend beyond the calculated value (see closed-loop bw plots, figures 15 and 27). as a rule of thumb, capacitor c f will not be required if: ( r f i r g ) c i ng 4 w o where ng is the noise gain (1 + r f /r g ) of the circuit. for most voltage gain applications, this should be the case. pulse response unlike a traditional voltage feedback amplifier, where the slew speed is dictated by its front end dc quiescent current and gain bandwidth product, the ad9631 and ad9632 provide on de- mand current that increases proportionally to the input step signal amplitude. this results in slew rates (1300 v/ m s) compa- rable to wideband current feedback designs. this, combined with relatively low input noise current (2.0 pa/ ? hz ), gives the ad9631 and ad9632 the best attributes of both voltage and current feedback amplifiers. large signal performance the outstanding large signal operation of the ad9631 and ad9632 is due to a unique, proprietary design architecture. in order to maintain this level of performance, the maximum 550 v-mhz product must be observed, (e.g., @ 100 mhz, v o 5.5 v p-p). power supply bypassing adequate power supply bypassing can be critical when optimiz- ing the performance of a high frequency circuit. inductance in the power supply leads can form resonant circuits that produce peaking in the amplifiers response. in addition, if large current transients must be delivered to the load, then bypass capacitors (typically greater than 1 m f) will be required to provide the best settling time and lowest distortion. a parallel combination of at least 4.7 m f, and between 0.1 m f and 0.01 m f, is recommended. some brands of electrolytic capacitors will require a small series damping resistor ? 4.7 w for optimum results. driving capacitive loads the ad9631 and ad9632 were designed primarily to drive nonreactive loads. if driving loads with a capacitive component is desired, the best frequency response is obtained by the addi- tion of a small series resistance as shown in figure 60. the ac- companying graph shows the optimum value for r series vs. capacitive load. it is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll-off of r series and c l . r f r series r l 1k w c l r in ad9631/32 r in figure 60. driving capacitive loads 40 0 25 30 10 5 20 15 20 10 r series ? w c l ?pf figure 61. recommended r series vs. capacitive load
ad9631/ad9632 rev. a C15C applications the ad9631 and ad9632 are voltage feedback amplifiers well suited for such applications as photodetectors, active filters, and log amplifiers. the devices wide bandwidth (320 mhz), phase margin (65 ), low noise current (2.0 pa/ ? hz ), and slew rate (1300 v/ m s) give higher performance capabilities to these appli- cations over previous voltage feedback designs. with a settling time of 16 ns to 0.01% and 11 ns to 0.1%, the devices are an excellent choice for dac i/v conversion. the same characteristics along with low harmonic distortion make them a good choice for adc buffering/amplification. with su- perb linearity at relatively high signal frequencies, the ad9631 and ad9632 are ideal drivers for adcs up to 12 bits. operation as a video line driver the ad9631 and ad9632 have been designed to offer out- standing performance as video line drivers. the important specifications of differential gain (0.02%) and differential phase (0.02 ) meet the most exacting hdtv demands for driving video loads. 75 w cable 274 w 274 w 75 w cable 75 w 75 w v out +v s ? s 75 w v in 0.1 m f 10 m f ad9631/ ad9632 3 2 7 0.1 m f 10 m f 4 6 figure 62. video line driver active filters the wide bandwidth and low distortion of the ad9631 and ad9632 are ideal for the realization of higher bandwidth active filters. these characteristics, while being more common in many current feedback op amps, are offered in the ad9631 and ad9632 in a voltage feedback configuration. many active filter configu- rations are not realizable with current feedback amplifiers. a multiple feedback active filter requires a voltage feedback amplifier and is more demanding of op amp performance than other active filter configurations such as the sallen-key. in general, the amplifier should have a bandwidth that is at least ten times the bandwidth of the filter if problems due to phase shift of the amplifier are to be avoided. figure 63 is an example of a 20 mhz low pass multiple feed- back active filter using an ad9632. 1 5 v in r4 154 w c1 50 pf c2 100pf r1 154 w ad9632 r3 78.7 w 0.1 m f +5v ? v 0.1 m f 7 3 2 4 100 w 6 v out 10 m f 10 m f figure 63. active filter circuit choose: f o = cutoff frequency = 20 mhz a = damping ratio = 1/q = 2 h = absolute value of circuit gain = r 4 r 1 = 1 then: k = 2 p f o c 1 c 2 = 4 c 1( h + 1) a 2 r 1 = a 2 hk r 3 = a 2 k ( h + 1) r 4 = h ( r 1)
ad9631/ad9632 rev. a C16C a/d converter driver as a/d converters move toward higher speeds with higher reso- lutions, there becomes a need for high performance drivers that will not degrade the analog signal to the converter. it is desir- able from a systems standpoint that the a/d be the element in the signal chain that ultimately limits overall distortion. this places new demands on the amplifiers used to drive fast, high resolution a/ds. with high bandwidth, low distortion and fast settling time the ad9631 and ad9632 make high performance a/d drivers for advanced converters. figure 64 is an example of an ad9631 used as an input driver for an ad872. a 12-bit, 10 msps a/d converter. msb bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit10 bit11 bit12 av dd agnd v ina ref gnd ref in ref out av ss av ss agnd otr clk drgnd drv dd dgnd dv dd 19 18 17 16 15 14 13 12 11 10 9 8 24 25 3 26 28 27 1 20 21 23 22 6 7 4 5 v inb 0.1 m f ?v analog ad872 1 7 6 4 3 2 5 1 m f +5v analog ad9631 analog in 0.1 m f 0.1 m f 0.1 m f digital output 0.1 m f 0.1 m f 10 w 49.9 w clock input 0.1 m f 0.1 m f 140 w +5v analog +5v digital +5v digital 130 w ?v analog 2 10 m f 10 m f figure 64. ad9631 used as driver for an ad872, a 12-bit, 10 msps a/d converter
ad9631/ad9632 rev. a C17C r f r o in +v s ? s r s r t r g out c1 1000pf c3 0.1 m f c5 10 m f c2 1000pf c4 0.1 m f c6 10 m f +v s ? s optional r f r o in +v s ? s r t r g out r s inverting configuration noninverting configuration supply bypassing figure 65. inverting and noninverting configurations for evaluation boards table i. ad9631a ad9632a gain gain component C1 +1 +2 +10 +100 C1 +2 +10 +100 r f 274 w 140 w 274 w 2 k w 2 k w 274 w 274 w 2 k w 2 k w r g 274 w 274 w 221 w 20.5 w 274 w 274 w 221 w 20.5 w r o (nominal) 49.9 w 49.9 w 49.9 w 49.9 w 49.9 w 100 w 100 w 49.9 w 49.9 w r s 100 w 130 w 100 w 100 w 100 w 100 w 100 w 100 w 100 w r t (nominal) 61.9 w 49.9 w 49.9 w 49.9 w 49.9 w 61.9 w 49.9 w 49.9 w 49.9 w small signal bw (mhz) 90 320 90 10 1.3 250 250 20 3 layout considerations the specified high speed performance of the ad9631 and ad9632 requires careful attention to board layout and compo- nent selection. proper rf design techniques and low pass para- sitic component selection are mandatory. the pcb should have a ground plane covering all unused por- tions of the component side of the board to provide a low im- pedance path. the ground plane should be removed from the area near the input pins to reduce stray capacitance. chip capacitors should be used for the supply bypassing (see figure 64). one end should be connected to the ground plane and the other within 1/8 inch of each power pin. an additional large (0.47 m fC10 m f) tantalum electrolytic capacitor should be connected in parallel, though not necessarily so close, to supply current for fast, large signal changes at the output. the feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. capacitance variations of less than 1 pf at the in- verting input will significantly affect high speed performance. stripline design techniques should be used for long signal traces (greater than about 1 inch). these should be designed with a characteristic impedance of 50 w or 75 w and be properly termi- nated at each end. evaluation board an evaluation board for both the ad9631 and ad9632 is avail- able that has been carefully laid out and tested to demonstrate that the specified high speed performance of the device can be realized. for ordering information, please refer to the ordering guide. the layout of the evaluation board can be used as shown or serve as a guide for a board layout.
ad9631/ad9632 rev. a C18C figure 66. evaluation board silkscreen (top) dip (n) inverter soic (r) inverter dip (n) inverter soic (r) inverter dip (n) noninverter soic (r) noninverter dip (n) noninverter soic (r) noninverter figure 67. board layout (solder side)
ad9631/ad9632 rev. a C19C figure 68. board layout (component side) dip (n) inverter soic (r) inverter dip (n) noninverter soic (r) noninverter
ad9631/ad9632 rev. a C20C outline dimensions dimensions shown in inches and (mm). c1936aC2.5C11/94 printed in u.s.a. 8-pin plastic dip (n package) pin 1 0.280 (7.11) 0.240 (6.10) 4 5 8 1 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) min 0.210 (5.33) max 0.160 (4.06) 0.115 (2.93) 0.430 (10.92) 0.348 (8.84) seating plane 0.022 (0.558) 0.014 (0.356) 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 8-pin plastic soic (r package) 0.019 (0.48) 0.014 (0.36) 0.050 (1.27) bsc 0.102 (2.59) 0.094 (2.39) 0.197 (5.01) 0.189 (4.80) 0.010 (0.25) 0.004 (0.10) 0.098 (0.2482) 0.075 (0.1905) 0.190 (4.82) 0.170 (4.32) 0.030 (0.76) 0.018 (0.46) 10 0 0.090 (2.29) 8 0 0.020 (0.051) x 45 chamf 1 8 5 4 pin 1 0.157 (3.99) 0.150 (3.81) 0.244 (6.20) 0.228 (5.79) 0.150 (3.81) 8-pin cerdip (q package) 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 15 0 0.005 (0.13) min 0.055 (1.4) max 1 pin 1 4 5 8 0.310 (7.87) 0.220 (5.59) 0.405 (10.29) max 0.200 (5.08) max 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) seating plane 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.100 (2.54) bsc

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